1. Field of the Invention
The present invention generally relates to integrated circuit fabrication. In particular, the present invention relates to a method for fabricating a memory cell with a decreased overlap between the source region and gate of the memory cell to thereby decrease the capacitance thereof and render it immune to undesirable short channel effects.
2. Description of Related Art
The flash memory device is one kind of the EEPROM (Electrically Erasable Programmable Read-Only Memory) device which is erased by means of electric signals. FIGS. 1A-1D show a conventional method for fabricating a flash memory cell suited for application on a semiconductor substrate 1, either a P-type silicon wafer or a P-well formed in an N-type silicon wafer.
As shown in FIG. 1A, a tunnel oxide layer 10, a floating gate 11, an inter-gate dielectric layer 12, and a control gate 13 are sequentially formed on the semiconductor substrate 1. The tunnel oxide layer 10 may be a silicon oxide layer, for example, formed by thermal oxidation on the surface of the semiconductor substrate 1. The floating gate 11 and control gate 13 are made of polysilicon deposited by a LPCVD (Low-Pressure Chemical Vapor Deposition) process. The polysilicon is doped with impurities to increase the conductivity thereof. The inter-gate dielectric layer 12 comprises a three-layer oxide-nitride-oxide structure.
Photolithography and etching processes are then applied. The control gate 13, inter-gate dielectric layer 12, floating gate 11, and tunnel oxide 10 are subsequently patterned and etched to form a stacked gate 14 as depicted in FIG. 1B. In the drawing, the tunnel oxide 10 is shown overlying the substrate's surface to prevent the substrate 1 from implantation damage. Afterwards, a photoresist layer 100 is formed to cover the substrate 1 on one side of the stacked gate 14. By utilizing the photoresist layer 100 as a mask, impurities 15 are implanted into the substrate 1 to form a lightly-doped region 16. The impurities 15, such as arsenic ions, are implanted with a dosage of about 1E14cm.sup.-2 to 1E15cm.sup.-2 and at an energy of about 40KeV to 60KeV. Accordingly, the junction depth of the lightly-doped region 16 ranges from about 0.15.mu.m to 0.3.mu.m. The photoresist layer 100 is thereafter removed.
A drive-in process, such as that performed at a temperature of about 1000.degree. C. for about 60 minutes, is utilized to diffuse the implanted impurities within the lightly-doped region 16 to a predetermined depth, for example, between 0.5.mu.m and 0.6.mu.m. As depicted in FIG. 1C, the lightly-doped region 16 is driven to the deeper junction depth designated by reference numeral 17. Because the thermal drive-in process is isotropic, it is inevitable that lateral diffusion occurs. Therefore, an overlap between the lightly-doped region 17 and the stacked gate 14 is formed.
As is shown in FIG. 1D, impurities 18, such as arsenic ions, are implanted into the substrate 1, by using stacked gate 14 as masking, to form a pair of heavily-doped regions 19A and 19B, serving as a drain region and a source region of the memory cell, respectively. Note that the source region 19B is disposed within the lightly-doped region 17 enclosed thereby.
An electrical potential of about 7 volts is applied to the drain region 19A when programming the flash memory cell. This generates high energy hot electrons near the drain junction, while a gate voltage of about 10-13V applied to control gate 13 provides a vertical electric field to draw the hot electrons through the tunnel oxide layer 10 and inject them into the floating gate 11. The injected hot electrons will therefore increase the threshold voltage of the flash memory cell.
The Fowler-Nordheim effect is used if erasing the flash cell is needed. At such time, a voltage is applied to source 19B to drain off the electrons stored within floating gate 11 via tunnel oxide layer 10. However, this applied voltage is apt to cause a junction breakdown between the heavily-doped region 19B and substrate 1. Therefore, the lightly-doped region 17 is formed to envelope the source region 19B and increase the breakdown voltage between the lightly-doped region 17 and substrate 1.
However, this conventional method forms the lightly-doped region 17 by thermally driving the implanted impurities to the desired junction depth. Lateral diffusion, as mentioned above, not only increases the overlapping area between the lightly-doped region 17 and stacked gate 14 and the parasitic capacitance therebetween, it also reduces the effective channel length between the source region 19B and the drain region 19A which leads to the undesirable short channel effect. Thus, there is a need for a flash memory cell fabrication process which reduces the overlap between a source region and the stacked gate.